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<a name="details" id="details"></a><h2 class="groupheader">Overview</h2>
<div class="textblock"><p>This file contains routines for the Stream switch master and slave ports. </p>
<p>These are applicable for both the AIE and Shim tiles.</p>
<pre>
MODIFICATION HISTORY:</pre><pre>Ver   Who     Date     Changes
</p>
<hr/>
<p>
1.0  Naresh  03/14/2018  Initial creation
1.1  Naresh  07/11/2018  Updated copyright info
1.2  Hyun    10/03/2018  Added the event port select function
1.3  Hyun    10/10/2018  Use the mask write API
1.4  Nishad  12/05/2018  Renamed ME attributes to AIE
</pre> </div><table class="memberdecls">
<tr class="memitem:aa546559dcbc87a1b92e977a3010b7fe6"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xaietile__strm_8c.html#aa546559dcbc87a1b92e977a3010b7fe6">XAieTile_StrmConfigMstr</a> (<a class="el" href="struct_x_aie_gbl___tile.html">XAieGbl_Tile</a> *TileInstPtr, u8 Master, u8 Enable, u8 PktEnable, u8 Config)</td></tr>
<tr class="memdesc:aa546559dcbc87a1b92e977a3010b7fe6"><td class="mdescLeft">&#160;</td><td class="mdescRight">This API is used to configure the selected master port of the stream switch in the corresponding tile as per the parameters.  <a href="#aa546559dcbc87a1b92e977a3010b7fe6">More...</a><br/></td></tr>
<tr class="separator:aa546559dcbc87a1b92e977a3010b7fe6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac5f99afdfa9ac96f40054cfb022176c3"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xaietile__strm_8c.html#ac5f99afdfa9ac96f40054cfb022176c3">XAieTile_StrmConfigSlv</a> (<a class="el" href="struct_x_aie_gbl___tile.html">XAieGbl_Tile</a> *TileInstPtr, u8 Slave, u8 Enable, u8 PktEnable)</td></tr>
<tr class="memdesc:ac5f99afdfa9ac96f40054cfb022176c3"><td class="mdescLeft">&#160;</td><td class="mdescRight">This API is used to configure the selected slave port of the stream switch in the corresponding tile.  <a href="#ac5f99afdfa9ac96f40054cfb022176c3">More...</a><br/></td></tr>
<tr class="separator:ac5f99afdfa9ac96f40054cfb022176c3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a31fbbf1714f13116db7b87a6492d59f3"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xaietile__strm_8c.html#a31fbbf1714f13116db7b87a6492d59f3">XAieTile_StrmConfigSlvSlot</a> (<a class="el" href="struct_x_aie_gbl___tile.html">XAieGbl_Tile</a> *TileInstPtr, u8 Slave, u8 Slot, u8 Enable, u32 RegVal)</td></tr>
<tr class="memdesc:a31fbbf1714f13116db7b87a6492d59f3"><td class="mdescLeft">&#160;</td><td class="mdescRight">This API is used to configure the selected slot of the slave port in the stream switch of the corresponding tile.  <a href="#a31fbbf1714f13116db7b87a6492d59f3">More...</a><br/></td></tr>
<tr class="separator:a31fbbf1714f13116db7b87a6492d59f3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a13824db867fb73286019007222d86433"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xaietile__strm_8c.html#a13824db867fb73286019007222d86433">XAieTile_StrmConnectCct</a> (<a class="el" href="struct_x_aie_gbl___tile.html">XAieGbl_Tile</a> *TileInstPtr, u8 Slave, u8 Master, u8 SlvEnable)</td></tr>
<tr class="memdesc:a13824db867fb73286019007222d86433"><td class="mdescLeft">&#160;</td><td class="mdescRight">This API is used to connect the selected master port to the specified slave port of the stream switch.  <a href="#a13824db867fb73286019007222d86433">More...</a><br/></td></tr>
<tr class="separator:a13824db867fb73286019007222d86433"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a202fd6150fa35b2d0a1b1506d580037b"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xaietile__strm_8c.html#a202fd6150fa35b2d0a1b1506d580037b">XAieTile_ShimStrmMuxConfig</a> (<a class="el" href="struct_x_aie_gbl___tile.html">XAieGbl_Tile</a> *TileInstPtr, u32 Port, u32 Input)</td></tr>
<tr class="memdesc:a202fd6150fa35b2d0a1b1506d580037b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This API sets up the mux configuraiton for Shim.  <a href="#a202fd6150fa35b2d0a1b1506d580037b">More...</a><br/></td></tr>
<tr class="separator:a202fd6150fa35b2d0a1b1506d580037b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2f48c9b8909b470091e8a0aa45719ca4"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xaietile__strm_8c.html#a2f48c9b8909b470091e8a0aa45719ca4">XAieTile_ShimStrmDemuxConfig</a> (<a class="el" href="struct_x_aie_gbl___tile.html">XAieGbl_Tile</a> *TileInstPtr, u32 Port, u32 Output)</td></tr>
<tr class="memdesc:a2f48c9b8909b470091e8a0aa45719ca4"><td class="mdescLeft">&#160;</td><td class="mdescRight">This API sets up the mux configuraiton for Shim DMA.  <a href="#a2f48c9b8909b470091e8a0aa45719ca4">More...</a><br/></td></tr>
<tr class="separator:a2f48c9b8909b470091e8a0aa45719ca4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af980eee192aeefe24e85dcfbe73e23d5"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xaietile__strm_8c.html#af980eee192aeefe24e85dcfbe73e23d5">XAieTile_StrmEventPortSelect</a> (<a class="el" href="struct_x_aie_gbl___tile.html">XAieGbl_Tile</a> *TileInstPtr, u8 Port, u8 Master, u8 Id)</td></tr>
<tr class="memdesc:af980eee192aeefe24e85dcfbe73e23d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">This API sets up the event port in stream switch.  <a href="#af980eee192aeefe24e85dcfbe73e23d5">More...</a><br/></td></tr>
<tr class="separator:af980eee192aeefe24e85dcfbe73e23d5"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Function Documentation</h2>
<a class="anchor" id="a2f48c9b8909b470091e8a0aa45719ca4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
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          <td class="memname">void XAieTile_ShimStrmDemuxConfig </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_aie_gbl___tile.html">XAieGbl_Tile</a> *&#160;</td>
          <td class="paramname"><em>TileInstPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Port</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Output</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This API sets up the mux configuraiton for Shim DMA. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">TileInstPtr</td><td>- Pointer to the Tile instance. </td></tr>
    <tr><td class="paramname">Port,:</td><td>Should be one of XAIETILE_SHIM_STRM_DEM_SOUTH2, XAIETILE_SHIM_STRM_DEM_SOUTH3, XAIETILE_SHIM_STRM_DEM_SOUTH4, or XAIETILE_SHIM_STRM_DEM_SOUTH5 </td></tr>
    <tr><td class="paramname">Output,:</td><td>Should be one of XAIETILE_SHIM_STRM_DEM_PL, XAIETILE_SHIM_STRM_DEM_DMA, or XAIETILE_SHIM_STRM_DEM_NOC.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_aie_gbl___reg_shim_dem_cfg.html#a541521bdf32e12d46a40d791ad30265e">XAieGbl_RegShimDemCfg::CtrlOff</a>, <a class="el" href="struct_x_aie_gbl___reg_fld_attr.html#a95f0d60188c5baf7612b662f58a98617">XAieGbl_RegFldAttr::Lsb</a>, <a class="el" href="struct_x_aie_gbl___reg_fld_attr.html#a235949ebe8e30fb2b6ee52c0b3c6b760">XAieGbl_RegFldAttr::Mask</a>, <a class="el" href="struct_x_aie_gbl___reg_shim_dem_cfg.html#ae3b26db86263e58d01e462fa11d4e5a3">XAieGbl_RegShimDemCfg::Port</a>, <a class="el" href="struct_x_aie_gbl___tile.html#a7c04a73941e64980a264a9d529fbb571">XAieGbl_Tile::TileAddr</a>, and <a class="el" href="struct_x_aie_gbl___tile.html#aadd948557d2723faa0cf47419e7d8a6e">XAieGbl_Tile::TileType</a>.</p>

</div>
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<a class="anchor" id="a202fd6150fa35b2d0a1b1506d580037b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">void XAieTile_ShimStrmMuxConfig </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_aie_gbl___tile.html">XAieGbl_Tile</a> *&#160;</td>
          <td class="paramname"><em>TileInstPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Port</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Input</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This API sets up the mux configuraiton for Shim. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">TileInstPtr</td><td>- Pointer to the Tile instance. </td></tr>
    <tr><td class="paramname">Port,:</td><td>Should be one of XAIETILE_SHIM_STRM_MUX_SOUTH2, XAIETILE_SHIM_STRM_MUX_SOUTH3, XAIETILE_SHIM_STRM_MUX_SOUTH6, or XAIETILE_SHIM_STRM_MUX_SOUTH7 </td></tr>
    <tr><td class="paramname">Input,:</td><td>Should be one of XAIETILE_SHIM_STRM_MUX_PL, XAIETILE_SHIM_STRM_MUX_DMA, or XAIETILE_SHIM_STRM_MUX_NOC.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_aie_gbl___reg_shim_mux_cfg.html#ac403e47e14f1bf3a8219587621035e48">XAieGbl_RegShimMuxCfg::CtrlOff</a>, <a class="el" href="struct_x_aie_gbl___reg_fld_attr.html#a95f0d60188c5baf7612b662f58a98617">XAieGbl_RegFldAttr::Lsb</a>, <a class="el" href="struct_x_aie_gbl___reg_fld_attr.html#a235949ebe8e30fb2b6ee52c0b3c6b760">XAieGbl_RegFldAttr::Mask</a>, <a class="el" href="struct_x_aie_gbl___reg_shim_mux_cfg.html#ac2d716d690d9c03b4d1da01571d300c6">XAieGbl_RegShimMuxCfg::Port</a>, <a class="el" href="struct_x_aie_gbl___tile.html#a7c04a73941e64980a264a9d529fbb571">XAieGbl_Tile::TileAddr</a>, and <a class="el" href="struct_x_aie_gbl___tile.html#aadd948557d2723faa0cf47419e7d8a6e">XAieGbl_Tile::TileType</a>.</p>

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<a class="anchor" id="aa546559dcbc87a1b92e977a3010b7fe6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">void XAieTile_StrmConfigMstr </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_aie_gbl___tile.html">XAieGbl_Tile</a> *&#160;</td>
          <td class="paramname"><em>TileInstPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Master</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Enable</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>PktEnable</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Config</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This API is used to configure the selected master port of the stream switch in the corresponding tile as per the parameters. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">TileInstPtr</td><td>- Pointer to the Tile instance. </td></tr>
    <tr><td class="paramname">Master</td><td>- Master port ID value. </td></tr>
    <tr><td class="paramname">Enable</td><td>- Enable/Disable the master port (1-Enable,0-Disable).</td></tr>
    <tr><td class="paramname">PktEnable</td><td>- Enable/Disable the packet switching mode (1-Enable,0-Disable).</td></tr>
    <tr><td class="paramname">Config</td><td>- Config value to be used for circuit/packet sw. Applicable only when Enable==1. Bit encoding when PktEnable==1: 7-Drop header on packet, 6:3-Mask, 2:0-Arbiter Bit encoding when PktEnable==0: 7:5-Rsvd, 4:0-Slave port ID to which the master port need to connect to Use the macro "xaietile_strm.c::XAIETILE_STRSW_MPORT_CFGPKT()" to frame the 8-bit Config.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_aie_gbl___reg_strm_mstr.html#a3dd87bc3b5ee390532029c05c574d320">XAieGbl_RegStrmMstr::Config</a>, <a class="el" href="struct_x_aie_gbl___reg_strm_mstr.html#a4a2f1b1a8d1410c0b18d98c5676c8e7a">XAieGbl_RegStrmMstr::DrpHdr</a>, <a class="el" href="struct_x_aie_gbl___reg_fld_attr.html#a95f0d60188c5baf7612b662f58a98617">XAieGbl_RegFldAttr::Lsb</a>, <a class="el" href="struct_x_aie_gbl___reg_fld_attr.html#a235949ebe8e30fb2b6ee52c0b3c6b760">XAieGbl_RegFldAttr::Mask</a>, <a class="el" href="struct_x_aie_gbl___reg_strm_mstr.html#a1c52e0d0f8697302f28ec07c99ddf6ff">XAieGbl_RegStrmMstr::MstrEn</a>, <a class="el" href="struct_x_aie_gbl___reg_strm_mstr.html#a5447ad63c163d71f31a62535dcc25111">XAieGbl_RegStrmMstr::PktEn</a>, <a class="el" href="struct_x_aie_gbl___reg_strm_mstr.html#aed9c222904cdb80c972183cc798fe415">XAieGbl_RegStrmMstr::RegOff</a>, <a class="el" href="struct_x_aie_gbl___tile.html#a7c04a73941e64980a264a9d529fbb571">XAieGbl_Tile::TileAddr</a>, and <a class="el" href="struct_x_aie_gbl___tile.html#aadd948557d2723faa0cf47419e7d8a6e">XAieGbl_Tile::TileType</a>.</p>

<p>Referenced by <a class="el" href="xsock__clitest_8c.html#a0ddf1224851353fc92bfbff6f499fa97">main()</a>, and <a class="el" href="xaietile__strm_8h.html#a13824db867fb73286019007222d86433">XAieTile_StrmConnectCct()</a>.</p>

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<a class="anchor" id="ac5f99afdfa9ac96f40054cfb022176c3"></a>
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<div class="memproto">
      <table class="memname">
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          <td class="memname">void XAieTile_StrmConfigSlv </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_aie_gbl___tile.html">XAieGbl_Tile</a> *&#160;</td>
          <td class="paramname"><em>TileInstPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Slave</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Enable</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>PktEnable</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This API is used to configure the selected slave port of the stream switch in the corresponding tile. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">TileInstPtr</td><td>- Pointer to the Tile instance. </td></tr>
    <tr><td class="paramname">Slave</td><td>- Slave port ID value. </td></tr>
    <tr><td class="paramname">Enable</td><td>- Enable/Disable the slave port (1-Enable,0-Disable). </td></tr>
    <tr><td class="paramname">PktEnable</td><td>- Enable/Disable the packet switching mode (1-Enable,0-Disable).</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_aie_gbl___reg_fld_attr.html#a95f0d60188c5baf7612b662f58a98617">XAieGbl_RegFldAttr::Lsb</a>, <a class="el" href="struct_x_aie_gbl___reg_fld_attr.html#a235949ebe8e30fb2b6ee52c0b3c6b760">XAieGbl_RegFldAttr::Mask</a>, <a class="el" href="struct_x_aie_gbl___reg_strm_slv.html#a41833cff9869ee4d0169275f6a534761">XAieGbl_RegStrmSlv::PktEn</a>, <a class="el" href="struct_x_aie_gbl___reg_strm_slv.html#ace5a164bd5ff35c835c9d5207ef69bad">XAieGbl_RegStrmSlv::RegOff</a>, <a class="el" href="struct_x_aie_gbl___reg_strm_slv.html#a3d371af0904f6e966038f383d32c2982">XAieGbl_RegStrmSlv::SlvEn</a>, <a class="el" href="struct_x_aie_gbl___tile.html#a7c04a73941e64980a264a9d529fbb571">XAieGbl_Tile::TileAddr</a>, and <a class="el" href="struct_x_aie_gbl___tile.html#aadd948557d2723faa0cf47419e7d8a6e">XAieGbl_Tile::TileType</a>.</p>

<p>Referenced by <a class="el" href="xsock__clitest_8c.html#a0ddf1224851353fc92bfbff6f499fa97">main()</a>, and <a class="el" href="xaietile__strm_8h.html#a13824db867fb73286019007222d86433">XAieTile_StrmConnectCct()</a>.</p>

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<div class="memproto">
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        <tr>
          <td class="memname">void XAieTile_StrmConfigSlvSlot </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_aie_gbl___tile.html">XAieGbl_Tile</a> *&#160;</td>
          <td class="paramname"><em>TileInstPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Slave</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Slot</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Enable</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>RegVal</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<p>This API is used to configure the selected slot of the slave port in the stream switch of the corresponding tile. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">TileInstPtr</td><td>- Pointer to the Tile instance. </td></tr>
    <tr><td class="paramname">Slave</td><td>- Slave port ID value. </td></tr>
    <tr><td class="paramname">Slot</td><td>- Slave slot ID value, ranging from 0-3. </td></tr>
    <tr><td class="paramname">Enable</td><td>- Enable/Disable the slave slot (1-Enable,0-Disable).</td></tr>
    <tr><td class="paramname">RegVal</td><td>- Config value to be used for the slot. Applicable only when Enable==1, else set to 0. Bit encoding : 31:21-Rsvd, 28:24-Slot ID, 23:21-Rsvd, 20:16-ID mask, 15:6-Rsvd, 5:4-Master select/msel, 3-Rsvd, 2:0-Arbiter to use. Use the macro "xaietile_strm.c::XAIETILE_STRSW_SLVSLOT_CFG()" to frame the 32-bit RegVal.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_aie_gbl___reg_strm_slot.html#a2309be73a666b041ae8365440ac3d3df">XAieGbl_RegStrmSlot::En</a>, <a class="el" href="struct_x_aie_gbl___reg_fld_attr.html#a95f0d60188c5baf7612b662f58a98617">XAieGbl_RegFldAttr::Lsb</a>, <a class="el" href="struct_x_aie_gbl___reg_fld_attr.html#a235949ebe8e30fb2b6ee52c0b3c6b760">XAieGbl_RegFldAttr::Mask</a>, <a class="el" href="struct_x_aie_gbl___reg_strm_slot.html#afafe2554fa3c1a30e504ede26c78c7eb">XAieGbl_RegStrmSlot::RegOff</a>, <a class="el" href="struct_x_aie_gbl___tile.html#a7c04a73941e64980a264a9d529fbb571">XAieGbl_Tile::TileAddr</a>, and <a class="el" href="struct_x_aie_gbl___tile.html#aadd948557d2723faa0cf47419e7d8a6e">XAieGbl_Tile::TileType</a>.</p>

<p>Referenced by <a class="el" href="xsock__clitest_8c.html#a0ddf1224851353fc92bfbff6f499fa97">main()</a>.</p>

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          <td class="memname">void XAieTile_StrmConnectCct </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_aie_gbl___tile.html">XAieGbl_Tile</a> *&#160;</td>
          <td class="paramname"><em>TileInstPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Slave</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Master</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>SlvEnable</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This API is used to connect the selected master port to the specified slave port of the stream switch. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">TileInstPtr</td><td>- Pointer to the Tile instance. </td></tr>
    <tr><td class="paramname">Slave</td><td>- slave port ID value. </td></tr>
    <tr><td class="paramname">Master</td><td>- Master port ID value. </td></tr>
    <tr><td class="paramname">SlvEnable</td><td>- Enable/Disable the slave port (1-Enable,0-Disable).</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="xaietile__strm_8c.html#aa546559dcbc87a1b92e977a3010b7fe6">XAieTile_StrmConfigMstr()</a>, and <a class="el" href="xaietile__strm_8c.html#ac5f99afdfa9ac96f40054cfb022176c3">XAieTile_StrmConfigSlv()</a>.</p>

<p>Referenced by <a class="el" href="xsock__clitest_8c.html#a0ddf1224851353fc92bfbff6f499fa97">main()</a>.</p>

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          <td class="memname">void XAieTile_StrmEventPortSelect </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_aie_gbl___tile.html">XAieGbl_Tile</a> *&#160;</td>
          <td class="paramname"><em>TileInstPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Port</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Master</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Id</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This API sets up the event port in stream switch. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">TileInstPtr</td><td>- Pointer to the Tile instance. </td></tr>
    <tr><td class="paramname">Port,:</td><td>Port number. 0 to 7. </td></tr>
    <tr><td class="paramname">Master,:</td><td>1 for master. 0 for slave. </td></tr>
    <tr><td class="paramname">Id,:</td><td>Port ID for event generation</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_aie_gbl___reg_fld_attr.html#a95f0d60188c5baf7612b662f58a98617">XAieGbl_RegFldAttr::Lsb</a>, <a class="el" href="struct_x_aie_gbl___reg_fld_attr.html#a235949ebe8e30fb2b6ee52c0b3c6b760">XAieGbl_RegFldAttr::Mask</a>, <a class="el" href="struct_x_aie_gbl___reg_strm_evt_port.html#a79e9c25778cc7199f94e1e38d87d6a80">XAieGbl_RegStrmEvtPort::MstrSlv</a>, <a class="el" href="struct_x_aie_gbl___reg_strm_evt_port.html#add5ccd45ee1169795cd3dbc1dae55687">XAieGbl_RegStrmEvtPort::Port</a>, <a class="el" href="struct_x_aie_gbl___reg_strm_evt_port.html#a1a989b54530092602008a2e71493593a">XAieGbl_RegStrmEvtPort::RegOff</a>, <a class="el" href="struct_x_aie_gbl___tile.html#a7c04a73941e64980a264a9d529fbb571">XAieGbl_Tile::TileAddr</a>, and <a class="el" href="struct_x_aie_gbl___tile.html#aadd948557d2723faa0cf47419e7d8a6e">XAieGbl_Tile::TileType</a>.</p>

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